Generally speaking, computer systems typically include one or more central processor units (CPUs). Each CPU includes many signal paths that convey data between functional units that operate on that data. Such data is typically conveyed using a transfer cycle having a specified timing structure. That timing structure dictates a time period when the data to be transferred will be valid. Accordingly, the data is captured while it is valid and held for a specified amount of time. Such data capture can be performed using a number of edge triggered latches.
Within a CPU, edge triggered latches are commonly implemented using a circuit referred to as a xe2x80x9csense amplifierxe2x80x9d. Sense amplifiers are designed to sense the logic level of a data signal and to output a latched version of that logic level. Because the above mentioned time period is typically specified with respect to a particular clock cycle, an edge triggered latch typically samples or xe2x80x9csensesxe2x80x9d the data on the rising edge of that clock cycle. The data is latched, i.e. held at the output of the sense amplifier, until the falling edge of that clock cycle or until the rising edge of the next clock cycle, depending upon its design. Until the next rising edge of the clock, new data can be asserted on the signal line without affecting the latched data.
Logic circuits are typically connected to the input or output terminals of sense amplifiers such that a logic function is performed on the logic levels developed thereon. For example, logic circuits are typically connected to the input terminals of sense amplifiers to implement set and reset functions. In other words, those logic circuits cause the output terminals of the sense amplifier to develop logic high (set) or logic low (reset) levels in response to a pre-determined set of logic conditions.
One such logic circuit is a multiplexer circuit. The combination of a multiplexer and a sense amplifier is referred to as a xe2x80x9cmultiplexing differential sense amplifierxe2x80x9d or a mux latch. A mux latch senses the logic levels of data signals that are connected to its input terminals. A number of control signals are connected to the mux latch that indicate which of those input data signals is to have its logic level latched at the output of the sense amplifier.
In a typical mux latch configuration, a logic high level is permanently developed on a first data signal and a logic low level is permanently developed on a second data signal. When a first pre-determined set of logic conditions is encountered, the control signals indicate that the logic high level of the first data signal should be latched at the output of the sense amplifier. Accordingly, the logic high level is output from the multiplexer and latched at the output terminal of the sense amplifier, thereby setting it. Alternatively, when a second pre-determined set of logic conditions is encountered, the control signals indicate that the logic level of the second data signal should be latched at the output of the sense amplifier. Accordingly, the logic low level is output by the multiplexer and latched at the output terminal of the sense amplifier, thereby resetting it.
The use of a mux latch arrangement to set and reset the output terminals of a sense amplifier is not desirable. Such a mux latch typically includes a high input loading characteristic, develops a large amount of parasitic capacitance that affects the performance of the attached sense amplifier and includes inherent charge imbalances that affect its ability to quickly respond to the control signals connected thereto.
Other prior art solutions involve performing individual multiplexer operations on each data signal before it is connected to the sense amplifier. In other words, a multiplexer circuit is connected between each data signal and the sense amplifier. In response to pre-determined logic conditions, each multiplexer either outputs a logic high level, a logic low level, or the logic level of the, attached input data signal. The output of the multiplexer is conveyed to the sense amplifier such that the sense amplifier output terminals are set to a logic high level, reset to a logic low level or are responsive to the input data signals. However, such a configuration adds additional propagation delay from the time when data is asserted on the data signals until the resulting output data is generated by the sense amplifier, thereby reducing performance.
Accordingly, a method and apparatus for adding set and reset functions to a sense amplifier employed in a computer system. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The present invention allows set and reset functionality to be added to the sense amplifier in a manner that minimally impacts the performance of that sense amplifier.
In accordance with a first aspect of the present invention, a set and reset circuit is incorporated into a sense amplifier for setting or resetting the sense amplifier output terminals in response to assertions of set and reset control signals. When the set control signal is asserted, a first discharge path allows a charge stored on one of the output terminals to be discharged at a rate that is proportional to a voltage level developed on the set control signal. Alternatively, when the reset control signal is asserted, a second discharge path allows a charge stored on a second output terminal to be discharged at a rate that is proportional to a voltage level developed on the reset control signal.
When the set and reset control signals are de-asserted, the sense amplifier operates in a normal manner. Accordingly, the first discharge path discharges charge stored on one of the output terminals at a rate that is proportional to a voltage level developed on a first data signal. Also, the second discharge path discharges charge stored on the opposing one of the output terminals at a rate that is proportional to a voltage level developed on a second data signal that represents a logic level that is complementary to the logic level represented by the first data signal.
The set and reset circuit includes a high conductance characteristic such that the discharge paths can discharge the corresponding charges from the output terminals at a faster rate in proportion to the set or reset control signals, than in proportion to the data signals.
In a further embodiment of the invention, the sense amplifier includes an evaluate unit. The evaluate unit is connected to an electrical ground for conveying the charges developed on the first and second output terminals thereto through the respective discharge paths.
In a still further embodiment of the invention, the set and reset circuit includes a pair of conductive paths that are turned-on in response to an assertion of the set or reset control signals, respectively. Those conductive paths are connected in parallel with associated portions of the discharge paths such that effects imposed on those discharge paths due to the data signals can be overridden.
Accordingly, the present invention allows the output terminals of the sense amplifier to be set or reset without significantly affecting that sense amplifier""s performance.